The design and implementation of a low-power clock-powered microprocessor

We describe the design and implementation of a 16-bit clock-powered micropr ocessor that dissipates only 2.9 mW at 15.8 MHz based on laboratory measure ments. Clock-powered logic (CPL) has been developed as a new approach for d esigning and building low-power VLSI systems that exploit the benefits of s upply-voltage-scaled static CMOS and energy-recovery CMOS techniques. In CP L, the clock signals are a source of ac power for the other large on-chip c apacitive loads. Clock amplitude and waveform shape combine to reduce power , By exploiting energy recovery and an energy-conserving clock driver, it i s possible to build ultra-low-power CMOS processors with this approach. We compare the CPL approach with a conventional, fully dissipative approach fo r a processor with a similar ISA and VLSI architecture which was designed u sing the same set of VLSI CAD tools. The simulation results indicate that t he CPL microprocessor would dissipate 40% less power than the conventional design.