Low-power area-efficient high-speed I/O circuit techniques

We present a 4-Gb/s I/O circuit that fits in 0.1-mm(2) of die area, dissipa tes 90 mW of power, and operates over 1 m of 7-mil 0.5-oz PCB trace in a 0. 25-mum CMOS technology, Swing reduction is used in an input-multiplexed tra nsmitter to provide most of the speed advantage of an output-multiplexed ar chitecture with significantly lower power and area. A delay-locked loop (DL L) using a supply-regulated inverter delay line gives very low jitter at a fraction of the power of a source-coupled delay line-based DLL, Receiver ca pacitive offset trimming decreases the minimum resolvable swing to 8 mV, gr eatly reducing the transmission energy without affecting the performance of the receive amplifier, These circuit techniques enable a high level of I/O integration to relieve the pin bandwidth bottleneck of modern VLSI chips.