A 20-Gb/s CMOS multichannel transmitter and receiver chip set for ultra-high-resolution digital displays

A multichannel transmitter (TX) and receiver (RX) chip set operating at 20 Gb/s (5 Gb/s x 4 ch) has been developed by using 0.25-mum CMOS technology. To achieve multichannel data transmission and high-speed operation, the chi p set features: 1) circuits for compensating the phase difference between m ultiple RX chips, which is due to data skew resulting from different length s of transmission cables, and for compensating the frequency difference bet ween the system clocks of the TX and RX chips; 2) a self-alignment phase de tector with parallel output for a high-speed data-recovery circuit; and 3) a fully pipelined 8B10B encoder, At a 2.5-V power supply, the power consump tion of the TX chip during 5-Gb/s operation is 500 mW and that of the RX ch ip is 750 mW, Four of these TX/RX chip sets can provide an aggregate bandwi dth of 20 Gb/s.