A 2.4 gb/s/pin simultaneous bidirectional parallel link with per-pin skew compensation

This paper describes voltage and timing margins and design trade-offs in lo w-cost parallel links. Results from a transceiver prototype demonstrate tha t per-pin skew compensation improves timing margins in these parallel links and can be implemented with reasonable cost overhead. Single-ended and sim ultaneous bidirectional links are viable alternatives to the traditional di fferential and unidirectional systems-these links require fewer pins and wi res for the same bandwidth, and the additional noise sources, while signifi cant, can be managed by careful circuit and package design.