A 16-Mb 400-MHz loadless CMOS four-transistor SRAM macro

We have used a 5-metal 0.18-mum CMOS logic process to develop a 16-Mb 400-M Hz loadless CMOS four-transistor SRAM macro. The macro contains: 1) end-poi nt dual-pulse drivers for accurate timing control; 2) a wordline-voltage-le vel compensation circuit for stable data retention; and 3) an all-adjoining twisted bitline scheme for reduced bitline coupling capacitance. The macro is capable of 400-MHz high-speed access at 1.8-V supply voltage and is 66% the size of a conventional six-transistor SRAM macro. We have also develop ed a higher-performance 500-MHz loadless four-transistor SRAM macro in a CM OS process using 0.13-mum gate length.