A 0.18-mu m 256-mb DDR-SDRAM with low-cost post-mold tuning method for DLLreplica

Authors
Kuge, S Kato, T Furutani, K Kikuda, S Mitsui, K Hamamoto, T Setogawa, J Hamade, K Komiya, Y Kawasaki, S Kono, T Amano, T Kubo, T Haraguchi, M Nakaoka, Y Akiyama, M Konishi, Y Ozaki, H Yoshihara, T
Citation
S. Kuge et al., A 0.18-mu m 256-mb DDR-SDRAM with low-cost post-mold tuning method for DLLreplica, IEEE J SOLI, 35(11), 2000, pp. 1680-1689
Citations number
7
Categorie Soggetti
Eletrical & Eletronics Engineeing
Journal title
IEEE JOURNAL OF SOLID-STATE CIRCUITS
ISSN journal
00189200 → ACNP
Volume
35
Issue
11
Year of publication
2000
Pages
1680 - 1689
Database
ISI
SICI code
0018-9200(200011)35:11<1680:A0M2DW>2.0.ZU;2-R
Abstract
A 200-MHz double-data-rate synchronous-DRAM (DDR-SDRAM) was developed. The chip contains. a delay-locked loop (DLL) which performs over a wide range o f operating conditions. Post-mold-tuning allows precise replica programming . A 200-MHz intra-chip data bus is suitable for DDR operation.