A heterogeneous reconfigurable platform enables the flexible implementation
of baseband wireless functions at energy levels between 10 and 100 MOPS/mW
, six times higher than traditional digital signal processors. A 5.2 mm x 6
.7 mm prototype processor, targeted for voice compression, is implemented i
n a 0.25-mum 6-metal CMOS process, and consumes 1.8 mW at an average operat
ion rate of 40 MHz. It combines an embedded microprocessor with an array of
computational units of different granularities, connected by a hierarchica
l reconfigurable interconnect network.