A 60-MHz 240-mW MPEG-4 videophone LSI with 16-Mb embedded DRAM

A 240-mW single-chip MPEG-4 videophone LSI with a 16-Mb embedded DRAM is fa bricated utilizing a 0.25-mum CMOS triple-well quad-metal technology. The v ideophone LSI is applied to 3GPP 3G-324M video-telephony standard for IMT-2 000, and implements the MPEG-4 video SP@L1 codec, the AMR speech codec, and the ITU-T H.223 Annex B multiplexing/demultiplexing at the same time. Three 16-bit multimedia-extended RISC processors, dedicated hardware accele rators, and a 16-Mb embedded DRAM are integrated on a 10.84 mm X 10.84 mm d ie. It also integrates camera, display, audio, and network interfaces requi red for a mobile videophone terminal In addition to conventional low-power techniques, such as clock gating and parallel operation, some new low-power techniques are also employed. These include an embedded DRAM with optimized configuration, a low-power motion e stimator, and the adoption of the variable-threshold voltage CMOS (VT-CMOS) . The MPEG-4 videophone LSI consumes 240 mW at 60 MHz, which is only 22% th at for a conventional multichip design. Variable threshold voltage CMOS red uces standby leakage current to 26 muA, which is only 17% that for the conv entional CMOS design.