Multilevel k-way hypergraph partitioning

Citation
G. Karypis et V. Kumar, Multilevel k-way hypergraph partitioning, VLSI DESIGN, 11(3), 2000, pp. 285-300
Citations number
25
Categorie Soggetti
Eletrical & Eletronics Engineeing
Journal title
VLSI DESIGN
ISSN journal
1065514X → ACNP
Volume
11
Issue
3
Year of publication
2000
Pages
285 - 300
Database
ISI
SICI code
1065-514X(2000)11:3<285:MKHP>2.0.ZU;2-R
Abstract
In this paper, we present a new multilevel k-way hypergraph partitioning al gorithm that substantially outperforms the existing state-of-the-art K-PM/L R algorithm for multiway partitioning, both for optimizing local as well as global objectives. Experiments on the ISPD98 benchmark suite show that the partitionings produced by our scheme are on the average 15% to 23% better than those produced by the K-PM/LR algorithm, both in terms of the hyperedg e cut as well as the (K - 1) metric. Furthermore, our algorithm is signific antly faster, requiring 4 to 5 times less time than that required by K-PM/L R.