ADVANCES IN THE DESIGN OF THE TOTEM NEUROCHIP

The TOTEM neurochip has proved its viability as a system for real-time computation in HEP and space applications requiring high performance for event classification, data mining, and signal processing. ISA and VME boards integrating the TOTEM chip as a coprocessor have been made available to selected experimental groups which reported satisfactory results. This paper presents a new architectural solution yielding hig her performance and reduced silicon area, The on-chip computational st ructures have been entirely redesigned to take advantage of a novel ap proach to number representation that, at the cost of a provably bounde d approximation, leads to a much-reduced silicon area, lower power dis sipation, and faster computation. This approach is validated by simula tion results on experimental data, as presented in the paper.