Recoding input sets of a combinational circuit in FPGA-based design

A method of recoding specified input sets of a combinational circuit that h ad been designed on the basis of field programmable gate arrays (FPGA) is c onsidered. The method is based on construction of a code the variables of w hich are functions of a subset of input variables, and, moreover, distingui sh any pair of input sets that generate distinct output sets. By means of t he method, it is possible to take into account constraints on the number of input poles of the logical blocks occurring in an FPGA structure.