3-D packaging methodologies for microsystems

Issues associated with the packaging of microsystems in plastic and three-d imensional (3-D) body styles are discussed. The integration of a microsyste m incorporating a micromachined silicon membrane pump, into a 3-D plastic e ncapsulated vertical multichip module package (MCM-V) is described. Finite element techniques are used to analyze the encapsulation stress in the stru cture of the package. Cracks develop in the chip carrier due to thermomecha nical stress. Based on the results of a finite element design study, the st ructures of the chip carriers are modified to reduce their risk of cracking . Alternative low stress 3-D packaging methodologies based on chip on board and plastic leadless chip carriers are discussed.