Escape routing design to reduce the number of layers in area array packaging

High density multilayer substrate technologies are indispensable to accommo date high inputs/outputs (I/Os) fine pitch area array integrated circuits ( ICs), chip scale packages/ball grid arrays (CSP/BGAs) in the coming packagi ng generation. They must provide not only a high wiring density, but also a n acceptable low cost, short turn around time (TAT) and reliability. Reduct ion of the number of layers is expected to be a reasonable solution for the conflicting demands. General approaches to reduce the layer count have bee n to decrease the size of the routing line width and spacing. However, they need changes in the manufacturing processes and materials, causing an incr eased cost. From escape routing design viewpoint, effects of routing manner on the laye r count has been studied, A preferential routing creates specific pad geome try resulting in a high wiring efficiency. This effect can be estimated wit h an increase in the number of lines per layer routable as a contribution o f "the hybrid channel," depending on capture pad pitch-pad diameter-line wi dth-interline space relationship, It is one of remarkable ease recognized t hat, within one line per channel rule, the preferential routing can effect almost equivalent to that by two lines per channel on the wireability. Its better effect on cost and TAT can also be expected compared with the two th inner sized lines per channel rule, since nothing changed in both manufactu ring processes and materials is needed, This method is applicable immediate ly and lightly to packages and boards for assembly of the high I/O flip chi ps, CSPs, and BGAs.