Short-circuit energy dissipation modeling for submicrometer CMOS gates

A significant part of the energy dissipation in static complementary metal- oxide-semiconductor (CMOS) structures is due to short-circuit currents. In this paper, an accurate analytical model for the CMOS short-circuit energy dissipation is presented. First, the short-circuit energy dissipation of th e CMOS inverter is modeled. The derived model is based on analytical expres sions of the inverter output waveform which include the influences of both transistor currents and the gate to-drain coupling capacitance, Also, the e ffect of the short-circuiting transistor's gate-source capacitance on the s hort-circuit energy dissipation, is taken into account. The a-power law MOS model that considers the carriers' velocity saturation effect of submicrom eter devices is used. Second, the inverter model is extended to static CMOS gates by using reduction techniques of series- and parallel-connected tran sistors. The results produced by the suggested model for a commercial 0.8-m um process, show very good agreement with SPICE simulations.