Novel test pattern generators for pseudoexhaustive testing

Pseudoexhaustive testing of a combinational circuit involves applying all p ossible input patterns to all its individual output cones. The testing ensu res detection of all detectable multiple stuck-at faults in the circuit and all detectable combinational faults within individual cones. Test pattern generators based on coding theory principles are not tailored to a specific circuit as they do not utilize any structural information. They usually ge nerate test sets that are several orders ct magnitude larger than the minim um size pseudoexhaustive test set required for a specific circuit. In this paper, we describe hardware efficient test pattern generators that employ k nowledge of the circuit output cone structures for generating minimal test sets. Using our techniques, we have designed generators that generate minim um size test sets for the ISCAS benchmark circuits.