A dual precision IEEE floating-point multiplier

Citation
G. Even et al., A dual precision IEEE floating-point multiplier, INTEGRATION, 29(2), 2000, pp. 167-180
Citations number
12
Categorie Soggetti
Computer Science & Engineering
Journal title
INTEGRATION-THE VLSI JOURNAL
ISSN journal
01679260 → ACNP
Volume
29
Issue
2
Year of publication
2000
Pages
167 - 180
Database
ISI
SICI code
0167-9260(200009)29:2<167:ADPIFM>2.0.ZU;2-3
Abstract
A new algorithm for computing IEEE-compliant rounding is presented, called injection-based rounding. Injection-based rounding is simple and facilitate s using the same rounding circuitry for different precisions. We demonstrat e the usefulness of injection-based rounding in a design of an IEEE floatin g-point multiplier capable of performing either a double-precision multipli cation or a single-precision multiplication. The multiplier is designed to minimize hardware cost by using only a half-sized multiplication array and by sharing the rounding circuitry for both precisions. The latency of the m ultiplier is in single-precision two clock cycles and in double precision t he latency is three clock cycles, where each pipeline stage contains roughl y 15 logic levels. (C) 2000 Elsevier Science B.V. All rights reserved.