VLSI design of 1-D DWT architecture with parallel filters

Wavelet transform coding has been drawing much attention because of its abi lity to decompose images into a hierarchical structure that is suitable for adaptive processing in the transform domain. This paper presents an Effici ent VLSI design of one-dimensional direct discrete wavelet transform proces sor. The proposed architecture computes three DWT stages and uses four para llel filters. The architecture is simple and offers 16-bit precision on inp ut and output data. It is constituted of three basic units: one storage uni t, four filters, and a control unit. No memory or registers are used for st oring intermediate results. Furthermore, data scheduling and memory managem ent remain very simple. The end result is an efficient VLSI implementation with a reduced area cost compared to the conventional approaches. The archi tecture can compute DWT at a data rate of 7 x 10(6) samples/s corresponding to a typical clock speed of 7 MHz. The architecture is simulated and verif ied at the gate level in VLSI. Process parameters used were those of 0.6 mu m technology. The chip area is about 15.7 mm(2). (C) 2000 Elsevier Science B.V. All rights reserved.