A wafer fault diagnosis scheme

With the increasing complexity of VLSI systems, hardware testability struct ures are becoming more commonplace. Advances in technology have enabled sys tem on chips, and design for testability is necessary to handle such comple x designs. We present a fault diagnosis scheme with its application to wafe r scale testing. A simple test structure is given which determines the stat us of each die. With this test structure all dies can be tested in parallel and therefore a considerable saving in test time is achieved as compared w ith probe testing. The wafer testing scheme promises to be effective and pr actical.