WIDE-BAND COMPRESSIVE RECEIVER BASED ON ADVANCED SUPERCONDUCTOR AND SEMICONDUCTOR CIRCUITS

A novel compressive cryoreceiver architecture has been proposed combin ing analog HTS, cryoelectronic, and advanced high-speed GaAs and high- speed/low-power SOI CMOS semiconductor technologies. The proposed rece iver will rival the sensitivity of narrowband receivers while providin g unprecedented wideband instantaneous frequency coverage with very sm all size, weight, and power requirements. Future developments will ext end the bandwidth capability. HTS tapped-delay-line chirp filters are the enabling technology for these instantaneous bandwidths greater tha n 1 GHz. The filters support dispersive delays as long as 40 ns and ti me-bandwidth products in excess of 100 using a bonded/thinned-wafer te chnique to fabricate YBa2Cu3O7-partial derivative stripline structures on 125-mu m-thick, 5-cm-diam LaAlO3 substrates. The filters have prod uced better than -18-dB error sidelobes in a receiver configuration. P reliminary work toward SOI CMOS receiver ASICs is reported. These ASIC s will perform pulse detection, data thinning, and binary integration functions. Requirements for A/D converters are discussed.