A SINGLE-FLUX-QUANTUM DEMULTIPLEXER

Many applications of Single-Flux-Quantum (SFQ) circuits will rely on t he transfer of multi-Gigabit per second data streams from SFQ logic to semiconductor logic for further processing, The low output voltages o f superconducting circuits currently limit the data rate per channel t o a few GHz. We have designed and fabricated a SFQ demultiplexer to re duce data transfer clock rates. The demultiplexer uses clocked data di stribution through a binary tree architecture. The circuit was fabrica ted using era eight level Nb/AlOx/Nb process and tested at 4.2K.