HIGH-SPEED TESTING OF A 4-BIT RSFQ DECIMATION DIGITAL-FILTER

We have developed a high speed test scheme for RSFQ circuits, in order to measure the maximum clock frequency of a four-bit RSFQ decimation digital filter (simulated to be 11 GHz). Our high speed test requires only a low speed interface and standard low-cost measurement equipment . Three auxiliary test units built of simple RSFQ circuits are used. A circular TTL structure generates an on-chip high speed clock with fre quency adjustable from 4 to 16 GHz. A pseudo-random number generator w ith period 64 clock cycles provides parallel input to the filter. Fina lly, 12 four-bit acquisition shift registers collect output data. We h ave integrated all the above units on a single chip. The chip is initi alized at low speed, run at high speed, and read out at low speed. Our testing scheme Is superior to previously reported high-speed tests in the area of the added circuitry, in the requirements on high-speed in put/output, in control, and in the parameters of the measurement equip ment. The scheme can be easily adapted to test various RSFQ circuits.