FUNCTIONAL-MODELING OF RSFQ CIRCUITS USING VERILOG HDL

Circuit level simulation is too slow to be used for verification of fu nction and timing of large RSFQ circuits. The alternative, known from semiconductor digital circuit design, is simulating at the logic (gate ) instead of the circuit (transistor or junction) level. Using a hardw are description language (HDL) such as Verilog, it is possible to writ e a functional model of each of the RSFQ basic gates. A large RSFQ cir cuit composed of hundreds gates and thousands Josephson junction can t hen be simulated using standard semiconductor industry CAD tools. We h ave developed a library of Verilog models for over 15 basic RSFQ gates . We describe in detail our model for the DRO RSFQ cell. We show how t his model can be generalized for other more complex cells. Our library has been verified by employing it in the design of timing for three l arge RSFQ circuits.