DESIGN AND LOW-SPEED TESTING OF A 4-BIT RSFQ MULTIPLIER-ACCUMULATOR

We have designed and tested a four-bit RSFQ multiplier-accumulator, th e central component of our decimation digital filter. The circuit cons ists of 38 synchronous RSFQ cells of six types arranged into a rectang ular systolic array fed by one parallel input and one serial input. Ti ming is based on a counter-flow clock distribution scheme with a simul ated maximum clock frequency of 11 GHz. The circuit, fabricated at Hyp res, Inc., contains 1100 Josephson junctions, has power consumption le ss than 0.2 mW, and area less than 2.5 mm(2). The multiplier-accumulat or has been tested at low frequency demonstrating full functionality a nd stable operation over a 24 hour testing period. This four-bit multi plier accumulator is one of the largest reported RSFQ circuits verifie d experimentally to date.