COUNTING SFQ ANALOG-TO-DIGITAL CONVERTER RESULTS

We have characterized Nb analog to digital converters using a resistor coupled SFQ flip Bop counter and a latching destructive readout (DRO) , The counter used SFQ buffers between bits to provide isolation durin g destructive readout, We have measured parallel readout at sample rat es up to 125 MSPS, We have also successfully operated an ADC which has Josephson junction regulated flip flop gate and readout bias busses, Using a self-resetting gate (SRG) at the carry out of the counter, me have measured the hit error rates (BER) of the counters, A two junctio n SQUID quantizer, biased in the voltage state, was used to produce co rrelated SFQ pulses at each junction. The SRG outputs of two IQ bit co unters connected to the two quantizer outputs were compared. We measur ed a BER of similar to 5 x 10(-11) with the quantizer operating at 19 GHz. We believe the principle error source is the latching SRG.