DATA-DRIVEN SELF-TIMED RSFQ DIGITAL INTEGRATED-CIRCUIT AND SYSTEM

A novel asynchronous timing scheme, data-driven self-timing (DDST) is proposed and implemented in Rapid Single-Flux-Quantum (RSFQ) supercond uctive integrated circuits. In this asynchronous approach, the timing signals are generated from the data and no global clock is needed to d riven the RSFQ circuit and system. The essence of the self-timing sche me is to localize the system timing in order to avoid the overhead of global clock distribution, and to minimize the timing uncertainty. The DDST scheme has been applied to the design of a shift register, a dem ultiplexor, and a self-timed high speed digital test system. In this p aper, test results of a 4-bit DDST shift register and a high speed on- chip clock generator will be presented to demonstrate the successful D DST operation of RSFQ integrated circuits at a rate of 20 Gb/s.