Charge storage and interface states effects in Si-nanocrystal memory obtained using low-energy Si+ implantation and annealing

Thin SiO2 oxides implanted by very-low-energy (1 keV) Si ions and subsequen tly annealed are explored with regards to their potential as active element s of memory devices. Charge storage effects as a function of Si fluence are investigated through capacitance and channel current measurements. Capacit ance-voltage and source-drain current versus gate voltage characteristics o f devices implanted with a dose of 1x10(16) cm(-2) or lower exhibit clear h ysteresis characteristics at low electric field. The observed fluence depen dence of the device electrical properties is interpreted in terms of the im planted oxide structure. (C) 2000 American Institute of Physics. [S0003-695 1(00)05447-4].