A clock recovery circuit has been successfully tested at frequencies u
p to 20 GHz. This cell is designed for a rapid-single-flux-quantum (RS
FQ) telecommunication data switch. It serves to set the receiver clock
in phase with the incoming digital signal. The circuit consists of a
dc-to-SFQ converter, ring oscillator [(RO) is a closed-loop RSFQ Josep
hson transmission line], confluence buffer, and an 8-bit binary counte
r, The input signal transforms to SFQ pulses, and each pulse resets th
e phase of the ring oscillator, giving a locking time of 1 bit. Thus,
the pull-in (capture) range and hold-in (tracking) range are the same,
and strictly depend on the encoding of the input signal. This range i
s estimated to be about 1 GHz at frequency 20 GHz, if the sequence of
consecutive ONEs or ZEROs does not exceed 20 bits, The quality factor
Q(RO) of ring oscillator is about 2000, which gives a jitter of 50 fs
for a 35-junction RO, A sampling technique was used to demonstrate pha
se recovery (phase locking) with only one incoming pulse per 512 clock
periods. (C) 1997 American Institute of Physics.