Sf. Hsiao et al., Design and implementation of a novel linear-array DCT/IDCT processor with complexity of order log(2) N, IEE P-VIS I, 147(5), 2000, pp. 400-408
Citations number
11
Categorie Soggetti
Eletrical & Eletronics Engineeing
Journal title
IEE PROCEEDINGS-VISION IMAGE AND SIGNAL PROCESSING
A new linear-array architecture for computation of both the discrete cosine
transform (DCT) and the inverse DCT (IDCT) is derived fram the heterogeneo
us dependence graphs representing the factorised coefficient matrices in th
e matrix formulation of the recursive algorithm. Using the Kronecker produc
t representation of the order-recursive algorithm, it is observed that the
kernel operations of the DCT and IDCT can be merged together by proper inpu
t/output data reordering. The processor containing only O(log(2) N) stages
is fully pipelineable and easily scaleable to compute longer DCT/IDCTs with
transform length N to the power of two. Owing to the systematic matrix for
mulation and the corresponding efficient architectural design, the new DCT/
IDCT processor has the advantages of high-throughput rate and low hardware
cost. Furthermore, the power consumption can be reduced significantly by tu
rning off the operation of the arithmetic units whenever possible.