Algorithm-based low-power/high-speed Reed-Solomon decoder design

With the spread of Reed-Solomon (RS) codes to portable wireless application s, low-power RS decoder design has become important. This paper discusses h ow the Berlekamp Massey Decoding algorithm can be modified and mapped to ob tain a low-power architecture. In addition, architecture level modification s that speed-up the syndrome and error computations are proposed. Then the VLSI architecture and design of the proposed low-power/high-speed decoder i s presented, The proposed design is compared with a normal design that does not use these algorithm/architecture modifications. The power reduction wh en compared to the normal design is estimated. The results indicate a power reduction of about 40% or a speed-up of 1,34.