Design-for-testability techniques for detecting delay faults in CMOS/BiCMOS logic families

The delay fault testing in logic circuits is studied. It is shown that by d etecting delayed time response in a transistor circuit, two types of faults are detected: 1) faults which cause delayed transitions at the output node due to some open defects and 2) faults which cause an intermediate voltage level at the output node. A test circuit is presented which enables the co ncurrent detection of delay faults. The proposed delay fault testing circui t does not substantially degrade the speed of the circuit under test (CUT), Simulation results show that this technique fits any design style.