ACTion: Combining logic synthesis and technology mapping for MUX-based FPGAs

Technology mapping for Multiplexor (MUX) based field programmable gate arra ys (FPGAs) has widely been considered. Here, a new algorithm is proposed th at applies techniques from logic synthesis during technology mapping, i.e., the target technology is considered in the minimization process. Binary de cision diagrams (BDDs) are used as an underlying data structure combining b oth structural and functional properties. The algorithm uses local don't ca res obtained by a greedy algorithm. To evaluate a netlist, a fast technolog y mapper is used. Since most of the changes to a netlist are local, re-mapp ing can also be done locally, allowing a fast but reliable the approach to several previously published algorithms. In most cases these results can be further improved. Compared to SIS, an improvement of 23% for area and 18% for delay can be observed on average. (C) 2000 Elsevier Science B.V. All ri ghts reserved.