GaInP/GaAs collector-up tunneling-collector heterojunction bipolar transistors (C-up TC-HBTs): Optimization of fabrication process and epitaxial layer structure for high-efficiency high-power amplifiers

This paper describes a novel heterojunction bipolar transistor (HBT) struct ure, the collector-up tunneling-collector HBT (C-up TC-HBT), that minimizes the offset voltage V-CE,V-sat and the knee voltage V-k. In this device, a thin GaInP layer is used as a tunnel barrier at the base-collector (BC) jun ction to suppress hole injection into the collector, which results in small V-CE,V-sat Collector-up configuration is used because of the observed asym metry of the band discontinuity between GaInP and GaAs depending on growth direction, To minimize V-k, Ne optimized the epitaxial layer structure as w ell as the conditions of ion implantation into the extrinsic emitter and po st-implantation annealing, The best results were obtained when a 5-nm-thick 5 x 10(17)-cm(-3)-doped GaInP tunnel barrier with a 20-nm-thick undoped Ga As spacer was used at the BC junction, and when 2 x 10(12)-cm(-2) 50-keV B implantation was employed followed by 10-min annealing at 390 degreesC. Fab ricated 40 x 40-mum(2) C-up TC-HBTs showed almost zero V-CE,V-sat (<10 mV) and a very small V-k of 0.29 V at a collector current density of 4 kA/cm(2) which are much lower than those of a typical GaInP/GaAs HBT. The results i ndicate that the C-up TC- HBT's are attractive candidates for high-efficien cy high power amplifiers.