FinFET - A self-aligned double-gate MOSFET scalable to 20 nm

Citation
D. Hisamoto et al., FinFET - A self-aligned double-gate MOSFET scalable to 20 nm, IEEE DEVICE, 47(12), 2000, pp. 2320-2325
Citations number
13
Categorie Soggetti
Eletrical & Eletronics Engineeing
Journal title
IEEE TRANSACTIONS ON ELECTRON DEVICES
ISSN journal
00189383 → ACNP
Volume
47
Issue
12
Year of publication
2000
Pages
2320 - 2325
Database
ISI
SICI code
0018-9383(200012)47:12<2320:F-ASDM>2.0.ZU;2-5
Abstract
MOSFETs with gate length down to 17 nm are reported. To suppress the short channel effect, a novel self-aligned double-gate MOSFET, FinFET, is propose d, By using boron-doped Si0.4Ge0.6 as a gate material, the desired threshol d voltage was achieved for the ultrathin body device. The quasiplanar natur e of this new variant of the vertical double-gate MOSFETs can be fabricated relatively easily using the conventional planar MOSFET process technologie s.