Coulomb blockade memory using integrated single-electron transistor/metal-oxide-semiconductor transistor gain cells

A 3 x 3-bit Coulomb blockade memory cell array has been fabricated in silic on-on-insulator (SOT) material. In each cell, the Coulomb blockade effect i n a single-electron transistor is used to define two charge states. The cha rge is stored on a memory node of area 1 mum x 1 mum or 1 mum x 70 nm and i s sensed with gain by a metal-oxide-semiconductor transistor. The write/rea d operation for a selected cell within the array is demonstrated. The measu red states are separated by similar to 1000 electrons for the 1 mum x 1 mum memory node cell and by 60 electrons for the 1 mum x 70 nm memory node cel l. Single-electron transistor controlled operation persists up to a tempera ture of 65K.