Mechanical stress related instabilities in silicon under metal coverage

Mechanical stress related instabilities in silicon bulk material under inte grated circuits (ICs) metallization are investigated. The test structures b ased on Wheatstone bridge configuration in which two out of four resistors were covered by wide aluminum stripes were fabricated especially for this p urpose. Calculations based on the piezoresistance effect were utilized to e stimate the mechanical stress in the silicon substrate. Also, finite elemen t modeling (FEM) of the fabricated test structures has been performed, Both results, experimental and numerical, show that metallization involves an a dditional stress term in the silicon buffer. The piezoresistance can influe nce the matching characteristics of ICs and also produce a time-drift of IC performance due to the time-drift of mechanical stress. Resistance mismatc hing of more than 1000 ppm was measured when the resistors were covered by aluminum. A covered resistance drift of 245 ppm due to aluminum plastic def ormation was measured when heating tests were applied. Finally, the simulat ion results for the prediction of the stress levels in silicon covered with metal lines of various widths are presented. For a 4 mum-width aluminum li ne it was recognized a safe distance of 10 mum.