1 VSOINMOSFET with suppressed floating body effects

A partially depleted CMOS compatible SOI NMOSFET structure with suppressed floating body effects is proposed in this paper. The structure uses high do se Si implantation to reduce the carrier lifetime in the floating body regi on near the bottom channel/buried oxide interface and convert that region i nto an amorphous-polycrystalline one. The fabricated devices exhibit suppre ssed floating body effects without area penalty or other adverse effects. C haracterization results show that the fabricated devices are suitable for l ow power 1 V applications. (C) 2000 Elsevier Science Ltd. All rights reserv ed.