Modeling short channel effect on high-k and stacked-gate MOSFETs

Citation
J. Zhang et al., Modeling short channel effect on high-k and stacked-gate MOSFETs, SOL ST ELEC, 44(11), 2000, pp. 2089-2091
Citations number
10
Categorie Soggetti
Apllied Physucs/Condensed Matter/Materiales Science","Eletrical & Eletronics Engineeing
Journal title
SOLID-STATE ELECTRONICS
ISSN journal
00381101 → ACNP
Volume
44
Issue
11
Year of publication
2000
Pages
2089 - 2091
Database
ISI
SICI code
0038-1101(200011)44:11<2089:MSCEOH>2.0.ZU;2-R
Abstract
The roll-off of threshold voltage in deep submicron MOSFETs with high-k and stacked gate dielectrics is studied. A model to account for the fringing f ield effect on the high-k slacked layer dielectrics is proposed. The model predictions are compared with the two-dimensional device simulation. Good a greement between the model predictions and device simulation results has be en obtained. (C) 2000 Elsevier Science Ltd. All rights reserved.