The roll-off of threshold voltage in deep submicron MOSFETs with high-k and
stacked gate dielectrics is studied. A model to account for the fringing f
ield effect on the high-k slacked layer dielectrics is proposed. The model
predictions are compared with the two-dimensional device simulation. Good a
greement between the model predictions and device simulation results has be
en obtained. (C) 2000 Elsevier Science Ltd. All rights reserved.