Design of MOS-translinear multiplier/dividers in analog VLSI

A general framework for designing current-mode CMOS analog multiplier/divid er circuits based on the cascade connection of a geometric-mean circuit and a squarer/divider is presented. It is shown how both building blocks can b e readily obtained from a generic second-order MOS translinear loop. Variou s implementations are proposed, featuring simplicity, favorable precision a nd wide dynamic range. They can be successfully employed in a wide range of analog VLSI processing tasks. Experimental results of two versions, based on stacked and folded MOS-translinear loops and fabricated in a 2.4-mum CMO S process, are provided in order to verify the correctness of the proposed approach.