Design and analysis of digital ratioed compressors for inner product processing

Inner product calculations are often required in digital neural computing. The critical path of the inner product of two binary vectors is the carry p ropagation delay generated from individual product terms. In this work, two architectures to arrange digital ratioed compressors are presented to redu ce the carry propagation delay in the critical path. Besides, the carry pro pagation delay estimation of these compressor building blocks is derived an d compared. The theoretical analysis and Verilog simulation both indicate t hat one of the compressor building blocks we present here might offer a sub -optimal solution for the basic building blocks used in digital hardware re alization of the inner product computation.