The viability of the Psi -cell concept that has been proposed far CMOS embe
dded flash applications is examined as the CMOS dimensions shrink down. Mor
e specifically, we focus on the dependence of the memory operation on the d
oping profile underneath the spacer, We show that for optimum operation of
the Psi -cell concept below 0.18 mum CMOS technologies, the S/D extension i
mplantation process step Should be omitted.