Early design stage exploration of fixed-length block structured architectures

An important challenge concerning the design of future microprocessors is t hat current design methodologies are becoming impractical due to long simul ation runs and due to the fact that chip layout considerations are not inco rporated in early design stages. In this paper, we show that statistical mo deling can be used to speed up the architectural simulations and is thus vi able for early design stage explorations of new microarchitectures. In addi tion, we argue that processor layouts should be considered in early design stages in order to tackle the growing importance of interconnects in future technologies. In order to show the applicability of our methodology which combines statistical modeling and processor layout considerations in an ear ly design stage, we have applied our method on a novel architectural paradi gm, namely a fixed-length block structured architecture. A fixed-length blo ck structured architecture is an answer to the scalability problem of curre nt architectures. Two important factors prevent contemporary out-of-order a rchitectures from being scalable to higher levels of parallelism in future deep-submicron technologies: the increased complexity and the growing domin ation of interconnect delays. In this paper, we show by using statistical m odeling and processor layout considerations, that a fixed-length block stru ctured architecture is a viable architectural paradigm for future microproc essors in future technologies thanks to the introduction of decentralizatio n and a reduced register file pressure. (C) 2000 Elsevier Science B.V. All rights reserved.