The MAJC architecture: A synthesis of parallelism and scalability

Authors
Tremblay, M Chan, J Chaudhry, S Conigliaro, AW Tse, SS
Citation
M. Tremblay et al., The MAJC architecture: A synthesis of parallelism and scalability, IEEE MICRO, 20(6), 2000, pp. 12-25
Citations number
12
Categorie Soggetti
Computer Science & Engineering
Journal title
IEEE MICRO
ISSN journal
02721732 → ACNP
Volume
20
Issue
6
Year of publication
2000
Pages
12 - 25
Database
ISI
SICI code
0272-1732(200011/12)20:6<12:TMAASO>2.0.ZU;2-C
Abstract
THE MAJC ARCHITECTURE ENHANCES APPLICATION PERFORMANCE BY EXPLOITING PARALL ELISM AT MULTIPLE LEVELS-INSTRUCTION, DATA, THREAD, AND PROCESS. SUPPORTING VERTICAL MULTITHREADING, SPECULATIVE MULTITHREADING, AND CHIP MULTIPROCESS ORS, THE SCALABLE VLIW ARCHITECTURE IS ALSO CAPABLE OF ADVANCED SPECULATION AND PREDICATION AND TREATS ALL DATA TYPES SIMILARLY.