Parallelization methodology for video coding - An implementation on the TMS320C80

This paper presents a parallelization methodology for video coding based on the philosophy of hiding as much communications by computation as possible , It models the task/data size, processor cache capacity, and communication contention, through a systematic decomposition and scheduling approach. Wi th the aid of Petri-nets and task graphs for representation and analysis, i t employs a triple buffering scheme to enable the functions of frame captur e, management, and coding to be performed in parallel. The theoretical spee dup analysis indicates that this method offers excellent communication hidi ng, resulting in system efficiency well above 90%. To prove its practicalit y, a H.261 video encoder has been implemented on a TMS320C80 system using t he method. Its performance was measured, from which the speedup and efficie ncy figures were calculated. The only difference detected between the theor etical and measured data is the program control overhead that has not been accounted for in the theoretical model. Even with this, the measured speedu p of the H.261 is 3.67 and 3.76 on four parallel processors (PPs) for QCIF and 352 x 240 video, respectively, which correspond to frame rate of 30.7 a nd 9.25 frames per second, and system efficiency of 91.8 % and 94 %, respec tively. This method is particularly efficient for platforms with small numb er of parallel processors.