Residual thermomechanical stresses in thinned-chip assemblies

A new technology for the three-dimensional (3-D) stacking of very thin chip s on a substrate is currently under development within the ultrathin chip s tacking (UTCS) Esprit Project 24910, In this work, we present the first-lev el UTCS structure and the analysis of the thermomechanical stresses produce d by the manufacturing process, Chips are thinned up to 10 or 15 mum We dis cuss potentially critical points at the edges of the chips, the suppression of delamination problems of the peripheral dielectric matrix and produce a comparative study of several technological choices for the design of metal lic interconnect structures. The purpose of these calculations is to give i nputs for the definition of design rules for this technology. We have there fore undertaken a programme that analyzes the influence of sundry design pa rameters and alternative development options. Numerical analyses are based on the finite element method.