Ternary static latch circuit

A new voltage-mode ternary CMOS static latch circuit is presented. Realized in a standard digital CMOS fabrication technology, this latch uses only en hancement-mode NMOS and PMOS transistors with single threshold voltage valu es. No special transistor threshold voltages or depletion-mode devices are required. Experimental data verify the ternary latch's operation. Fastest a nd slowest on-chip setup and hold times are simulated to be approximately 1 .9 ns and 3.4 ns, respectively, using data for standard 2 micron digital CM OS fabrication technologies.