A specification refinement methodology for power efficient partitioning ofdata-dominated algorithms within performance constraints

A specification refinement methodology for the power efficient partitioning of real-time data-dominated algorithms is presented. The main idea of the proposed methodology is the reorganization with respect to data transfer an d storage of the initial description of the target algorithm before convent ional partitioning. This is achieved through the application of data transf er and storage optimizing high-level code transformations to the initial de scription of the target algorithm. These transformations basically align th e data production and consumption between the different procedures of the i nitial specification thus reducing the memory size requirements of the syst em's realizations especially those in the interfaces between different proc essors. In this way the data transfer and storage related power consumption which forms an important part of the total power budget of a data dominate d system is significantly reduced. Performance issues are explicitly taken into account during the application of the data transfer and storage high-l evel transformations. The proposed methodology can be applied both in a par allel (programmable) processor context and also in heterogeneous hardware-s oftware architectures. The proposed methodology can be also used for the po wer efficient implementation of data dominated algorithms on architectures based on programmable cores and application specific memory hierarchies. Ex perimental results from real life applications prove the impact of the prop osed methodology.