Integration challenges in sub-0.25 mu m CMOS-based technologies

Market demands, which require increased functionality at lower costs are dr iving the development of high performance CMOS technologies with very high integration density. These demands are pushing the continuous scaling down of technologies and are resulting in a progressive acceleration of the rate of introduction of new technology generations. Current research and development activities in CMOS technology are focused on scaling CMOS technologies below 0.25 mum dimensions. While some of the p rocess modules can be scaled down in a conventional way, in some cases seve re limitations are reached and it is necessary to introduce major modificat ions to the process flow. In this paper we will present an overview of the main considerations to be kept in mind when scaling down to a 0.18 or 0.13 mum CMOS technology genera tion. (C) 2000 Elsevier Science Ltd. All rights reserved.