A general method in synthesis of pass-transistor circuits

A general method in synthesis and signal arrangement in different pass-tran sistor network topologies is analyzed. Several pass-transistor logic famili es have been introduced recently, but no systematic synthesis method is ava ilable that takes into account the impact of signal arrangement on circuit performance. In this paper we develop a Karnaugh map based method that can be used to efficiently synthesize pass-transistor logic circuits, which hav e balanced loads on true and complementary input signals. The method is app lied to the generation of basic two-input and three-input logic gates in CP L, DPL and DVL. The method is general and can be extended to synthesize any pass-transistor network. (C) 2000 Elsevier Science Ltd. All rights reserve d.