Study of the DC biasing effect on insertion losses in high-frequency interconnections

The paper deals with an experimental investigation of the behavior of high- frequency Si/SiO2/Al based interconnects when an extra DC bias voltage is a pplied, by means of which the conductor line changes the surface properties of the semiconductor substrate. By superposing a DC bias to the high-speed signal applied to the line, the insertion losses caused by the semiconduct or substrate show a significant decrease over the observed frequency range. In order to study this effect a number of test samples containing several microstrip asymmetric transmission lines were prepared and measured. The ob tained results suggest a way of controlling the performance and energy prop agation of interconnects on semiconductor substrates. The observed effect c an be successfully applied in high-speed blocks with tunable parameters. (C ) 2000 Elsevier Science Ltd. All rights reserved.