We demonstrate two-dimensional mapping of pn junctions in transistors by el
ectron holography. The source and drain areas in phase images of 0.3 mum CM
OS transistors can be delineated with the correct sign of the potential cha
nge, thus enabling a distinction between NMOS and PMOS devices in TEM holog
raphy. Measurements of samples containing abrupt boron marker layers establ
ish a spatial resolution of 5 nm for mapping the electrostatic potential di
stribution across pn junctions.